1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory device, and more particularly to a non-volatile semiconductor memory device with reduced errors on reading information stored in a flash memory.
2. Description of the Related Art
Known non-volatile semiconductor memory devices include an NAND cell-type flash memory. The NAND cell-type flash memory comprises a memory cell array including a plurality of NAND cell units. An NAND cell unit includes a plurality of memory cells serially connected, and two selection transistors connected to both ends thereof. A memory cell in an erased state holds “1”-data with a negative threshold voltage. At the time of data write, electrons are injected into a floating gate, thereby rewriting the data “0” with a positive threshold voltage. The NAND cell-type flash memory is only capable of shifting the threshold voltage from a lower one to a higher one at the time of data write. The reverse shift (from a higher threshold voltage to a lower one) can be executed only in an erase operation on a block basis.
In general, the NAND cell-type flash memory exhibits variations in the oxide film contained in memory cells on a memory cell basis and causes a distribution of threshold voltages at the time of write. In order to prevent failed information read at the time of read, therefore, threshold voltage levels are so set as to prevent overlapping threshold distributions. In the NAND cell-type flash memory, however, leakage of charge from the floating gate due to a variation over time, and deterioration of the oxide film due to iterative write and erase operations in the memory cell may vary and extend the threshold distributions to cause failed information read.
U.S. Pat. No. 5,657,332 discloses, for handling this problem, a method of changing a threshold voltage level for read at the time of occurrence of a read error, that is, failed information read, and executing another read operation.